distinct bit


Circuit Design with VHDL, third edition (The MIT Press), p.5

The symbol for an address decoder is presented in figure 1.4. The inputs are the address vector (a) plus an enable signal (ena). The output (b) is the signal that will activate one of the memory lines, so only one bit is different from all the others at a time (in this example, the distinct bit is 1, but it could be 0).