pp.251-252
これがトップファイル:
library ieee; use ieee.std_logic_1164.all; entity adder is generic( POLARITY : std_logic := '0'; -- この定数で.adder_unsigned、.adder_signedのどちらかを指定する。 NUM_BITS : natural := 4 ); port( a, b : in std_logic_vector(NUM_BITS-1 downto 0); sum : out std_logic_vector(NUM_BITS-1 downto 0) ); end entity; architecture rtl of adder is begin gen_adder : case POLARITY generate -- ラベル : case 式 generate when '0' => adder : entity work.adder_unsigned generic map (NUM_BITS) port map (a, b, sum); when others => adder : entity work.adder_signed generic map (NUM_BITS) port map (a, b, sum); end generate; end architecture;
これがadder_unsigned.vhdl
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity adder_unsigned is generic( -- 値はトップファイルのgeneric mapで指定するのでここでは指定しない。 WIDTH : natural ); port( in1, in2 : in std_logic_vector(WIDTH-1 downto 0); sum : out std_logic_vector(WIDTH-1 downto 0) ); end entity; architecture rtl of adder_unsigned is begin sum <= std_logic_vector(unsigned(in1) + unsigned(in2)); end architecture;
これがadder_signed.vhdl
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity adder_signed is generic( -- 値はトップファイルのgeneric mapで指定するのでここでは指定しない。 WIDTH : natural ); port( in1, in2 : in std_logic_vector(WIDTH-1 downto 0); sum : out std_logic_vector(WIDTH-1 downto 0) ); end entity; architecture rtl of adder_signed is begin sum <= std_logic_vector(signed(in1) + signed(in2)); end architecture;