プライオリティエンコーダー

Circuit Design with VHDL (The MIT Press)

/インコウダ/

p.249

半分まで読んでようやく実際の回路設計に入る。

VHDL 2008を指定しても全部が全部Quartusに実装されているわけではなかった。

library ieee;
use ieee.std_logic_1164.all;

entity priority_encoder is
    port(
        inp  : in  std_logic_vector(3 downto 0);
        outp : out std_logic_vector(3 downto 0)
    );
end entity;

architecture rtl of priority_encoder is
begin
    with inp select
        outp <= "1000" when "1111",
                "1000" when "1110",
                "1000" when "1101",
                "1000" when "1100",
                "1000" when "1011",
                "1000" when "1010",
                "1000" when "1001",
                "1000" when "1000",

                "0100" when "0111",
                "0100" when "0110",
                "0100" when "0101",
                "0100" when "0100",

                "0010" when "0011",
                "0010" when "0010",

                "0001" when "0001",

                "0000" when others;

/*
   -- VHDL 2008を指定したのにmatching selet statement (select?)が使えない。
   with inp select?
       outp <= "1000" when "1---",
               "0100" when "01--",
               "0010" when "001-",
               "0001" when "0001",
               "0000" when others;
*/
end architecture;