library ieee; use ieee.std_logic_1164.all; entity sute_vhdl is port ( x1: in std_logic; x2: in std_logic; s: in std_logic; f: out std_logic ); end entity; architecture rtl of sute_vhdl is begin /*process(x1, x2, s) begin if s = '0' then f <= x1; else f <= x2; end if; end process;*/ /*process(x1, x2, s) begin case s is when '0' => f <= x1; when others => f <= x2; end case; end process;*/ /*with s select f <= x1 when '0', x2 when others;*/ --論理ゲートをそのまま記述した例: --f <= (not s and x1) or (s and x2); --色々書けるがこれが素直で簡単。 f <= x1 when s = '0' else x2; end architecture;