pp.337-338
前回と同じステートマシンを別の方法で記述する。processを2つに分ける。最初のprocessには組み合わせ回路として状態テーブルを記述する。2つ目のprocessにはDフリップフロップを記述する。
library ieee; use ieee.std_logic_1164.all; entity sute_vhdl is port ( clock : in std_logic; aclr_n: in std_logic; w : in std_logic; z : out std_logic ); end entity; architecture behavior of sute_vhdl is type state_t is (A, B, C); signal state_present, state_next: state_t; begin process (w, state_present) begin case state_present is when A => if w = '0' then state_next <= A; else state_next <= B; end if; when B => if w = '0' then state_next <= A; else state_next <= C; end if; when C => if w = '0' then state_next <= A; else state_next <= C; end if; end case; end process; process (clock, aclr_n) begin if aclr_n = '0' then state_present <= A; elsif rising_edge(clock) then state_present <= state_next; end if; end process; z <= '1' when state_present = C else '0'; end architecture;