pp.561
今度は ↓ この回路のためのテストベンチ。シフトと加算と乗算だけで整数を3で割る回路である。アルゴリズムはまったく理解できない。
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity div_by_3 is port ( dividend: in unsigned(31 downto 0); quotient: out unsigned(31 downto 0) ); end entity; architecture rtl of div_by_3 is function div_by_three(dividend: unsigned(31 downto 0)) return unsigned is alias d is dividend; variable q, r: unsigned(31 downto 0); begin -- q is quotient, d is dividend q := (d srl 2) + (d srl 4); q := q + (q srl 4); q := q + (q srl 8); q := q + (q srl 16); r := resize(d - q * 3, 32); q := resize(q + (5 * (r + 1) srl 4), 32); return q; end function; begin quotient <= div_by_three(dividend); --quotient <= dividend/3; end architecture;