library ieee; use ieee.std_logic_1164.all; entity register_16_bit is port ( clk, load: in std_logic; d: in std_logic_vector(15 downto 0); q: out std_logic_vector(15 downto 0) ); end entity; architecture behavior of register_16_bit is begin reg: for i in 0 to 15 generate u: entity work.register_1_bit port map ( clk => clk, load => load, d => d(i), q => q(i) ); end generate; end architecture;