nビット加算器 / キャリールックアヘッドアダー / キャリーの遅延を見る -の続き。シミュレーターで動かなかったので書き直した。生成される回路は同じである。
ファイル一式: https://github.com/ti-nspire/VHDL_for_Quartus_Prime/tree/main/n_bits_adder_lookahead
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; entity n_bits_adder_lookahead is generic ( NUM_BITS: natural := 4 ); port ( c0: in std_logic; x, y: in std_logic_vector(NUM_BITS-1 downto 0); cout: out std_logic; s: out std_logic_vector(NUM_BITS-1 downto 0) ); end entity; architecture logic of n_bits_adder_lookahead is begin process(c0, x, y) variable g, p: std_logic_vector(NUM_BITS-1 downto 0) := (others => '0'); variable c: std_logic_vector(NUM_BITS downto 0) := (others => '0'); type term_t is array(1 to NUM_BITS) of std_logic_vector(NUM_BITS-1 downto 0); variable term: term_t := (others => (others => '0')); begin c(0) := c0; g := x and y; p := x or y; for i in term'range loop for j in 0 to i-1 loop if (j > 0) then term(i)(j) := and_reduce(p(i-1 downto j) & g(j-1)); else term(i)(0) := and_reduce(p(i-1 downto 0) & c(0)); end if; c(i) := or_reduce(g(i-1) & term(i)(j downto 0)); end loop; end loop; cout <= c(NUM_BITS); s <= x xor y xor c(x'range); end process; end architecture;
テストベンチ:
LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.numeric_std_unsigned.all; use ieee.numeric_std.all; ENTITY n_bits_adder_lookahead_vhd_tst IS END n_bits_adder_lookahead_vhd_tst; ARCHITECTURE n_bits_adder_lookahead_arch OF n_bits_adder_lookahead_vhd_tst IS -- constants -- signals SIGNAL c0 : STD_LOGIC; SIGNAL cout : STD_LOGIC; SIGNAL s : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL x : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL y : STD_LOGIC_VECTOR(3 DOWNTO 0); COMPONENT n_bits_adder_lookahead PORT ( c0 : IN STD_LOGIC; cout : OUT STD_LOGIC; s : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); x : IN STD_LOGIC_VECTOR(3 DOWNTO 0); y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ); END COMPONENT; BEGIN i1 : n_bits_adder_lookahead PORT MAP ( -- list connections between master ports and signals c0 => c0, cout => cout, s => s, x => x, y => y ); process begin for k in 0 to 1 loop for i in 0 to 15 loop for j in 0 to 15 loop c0 <= to_std_logic_vector(k, 1)(0); x <= to_std_logic_vector(i, 4); y <= to_std_logic_vector(j, 4); wait for 10 ns; end loop; end loop; end loop; wait; end process; END n_bits_adder_lookahead_arch;