BCD加算器 / 1桁

p.159-163
10進数1桁同士の加算器を作る。使うライブラリーが違う以外はほぼテキストのままである。
シミュレーション結果:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity adder_bcd_1_digit is
    port (
        x: in std_logic_vector(3 downto 0);
        y: in std_logic_vector(3 downto 0);
        s: out std_logic_vector(4 downto 0)
    );
end entity;

architecture rtl of adder_bcd_1_digit is
    signal z: unsigned(4 downto 0);
begin
    z <= unsigned('0' & x) + unsigned(y);
    s <= std_logic_vector(z) when z < 10 else std_logic_vector(z + 6);
end architecture;

テストベンチ:

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;            
use ieee.numeric_std_unsigned.all;
use ieee.numeric_std.all;         

ENTITY adder_bcd_1_digit_vhd_tst IS
END adder_bcd_1_digit_vhd_tst;
ARCHITECTURE adder_bcd_1_digit_arch OF adder_bcd_1_digit_vhd_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL s : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL x : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL y : STD_LOGIC_VECTOR(3 DOWNTO 0);
COMPONENT adder_bcd_1_digit
    PORT (
    s : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
    x : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    y : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
    );
END COMPONENT;
BEGIN
    i1 : adder_bcd_1_digit
    PORT MAP (
-- list connections between master ports and signals
    s => s,
    x => x,
    y => y
    );

process begin
    for i in 0 to 9 loop
    for j in 0 to 9 loop
        x <= to_std_logic_vector(i, 4);
        y <= to_std_logic_vector(j, 4);
        wait for 10 ns;
    end loop;
    end loop;
    wait;
end process;   
    
END adder_bcd_1_digit_arch;