Chapter 5
これでハードウェアは完成である。
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity hack is port ( test_load_pc: out std_logic; -- 確認用に外に出す。 reset: in std_logic; clk: in std_logic; in_port: in std_logic_vector(15 downto 0); -- 確認用にdipスイッチから値を入力できるようにする。 out_port: out std_logic_vector(15 downto 0); -- 確認用にDレジスタの出力を外に出す。 clk_out: out std_logic -- 確認用に外に出す。 ); end entity; architecture behavior of hack is signal temp_in_m: std_logic_vector(15 downto 0); signal temp_instruction: std_logic_vector(15 downto 0); signal temp_write_m: std_logic; signal temp_out_m: std_logic_vector(15 downto 0); signal temp_address_m: std_logic_vector(14 downto 0); signal temp_out_pc: std_logic_vector(15 downto 0); begin clk_out <= clk; cpu: entity work.cpu port map ( clk => clk, in_m => temp_in_m, instruction => temp_instruction, reset => reset, test_load_pc => test_load_pc, write_m => temp_write_m, out_m => temp_out_m, address_m => temp_address_m, out_pc => temp_out_pc, d_out => out_port ); memory: entity work.memory port map ( inp => temp_out_m, clk => clk, address => temp_address_m, load => temp_write_m, dip_sw => in_port, outp => temp_in_m ); rom: entity work.rom port map ( address => temp_out_pc, outp => temp_instruction ); end architecture;