コンピューターアーキテクチャー / CPUを作る

Chapter 5
全部組み合わせてCPUを作る。

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity cpu is
    port (
        clk: in std_logic;
        
        instruction: in std_logic_vector(15 downto 0);
        in_m: in std_logic_vector(15 downto 0);
        reset: in std_logic;
        
        out_m: out std_logic_vector(15 downto 0);
        write_m: out std_logic;
        address_m: out std_logic_vector(14 downto 0);
        out_pc: out std_logic_vector(15 downto 0);
        
        test_load_pc: out std_logic;
        
        d_out: out std_logic_vector(15 downto 0)
    );
end entity;

architecture behavior of cpu is
    signal alu_out: std_logic_vector(15 downto 0);
    signal a_reg_in, a_reg_out: std_logic_vector(15 downto 0);
    signal d_reg_in, d_reg_out: std_logic_vector(15 downto 0);
    signal alu_in_x, alu_in_y: std_logic_vector(15 downto 0);
    signal tempzx_tempnx_tempzy_tempny_tempf_tempno: std_logic_vector(5 downto 0);
    signal tempzr_tempng: std_logic_vector(1 downto 0);
    signal temp_load_a_reg, temp_load_d_reg, temp_load_pc: std_logic;
    signal temp_sel_mux_alu, temp_sel_a_m: std_logic;
begin
    test_load_pc <= temp_load_pc;
    d_out <= alu_in_x;

    mux_alu_inst: entity work.mux16
    port map (
        a => alu_out,
        b => instruction,
        sel => temp_sel_mux_alu,
        outp => a_reg_in
    );
    
    a_reg: entity work.register_16_bit
    port map (
        clk => clk,
        load => temp_load_a_reg,
        d => a_reg_in,
        q => a_reg_out
    );
    
    d_reg: entity work.register_16_bit
    port map (
        clk => clk,
        load => temp_load_d_reg,
        d => alu_out,
        q => alu_in_x
    );
    
    mux_a_m: entity work.mux16
    port map (
        a => a_reg_out,
        b => in_m,
        sel => temp_sel_a_m,
        outp => alu_in_y
    );
    
    alu: entity work.alu
    port map (
        x => alu_in_x,
        y => alu_in_y,
        
        zx_nx_zy_ny_f_no => tempzx_tempnx_tempzy_tempny_tempf_tempno,
        
        zr_ng => tempzr_tempng, 
        outp => alu_out
    );
    
    id: entity work.instruction_decoder
    port map (
        instruction => instruction,
        zr_ng => tempzr_tempng,
        
        load_a_reg => temp_load_a_reg,
        load_d_reg => temp_load_d_reg,
        load_pc => temp_load_pc,
        write_m => write_m,
        sel_alu_inst => temp_sel_mux_alu,
        sel_a_m => temp_sel_a_m,
        
        zx_nx_zy_ny_f_no => tempzx_tempnx_tempzy_tempny_tempf_tempno
    );
    
    pc: entity work.pc
    port map (
        inp => a_reg_out,
        clk => clk,
        inc => '1',
        load => temp_load_pc,
        reset => reset,
        outp => out_pc
    );
        
    address_m <= a_reg_out(14 downto 0);
    out_m <= alu_out;
 
end architecture;