基本ゲートを作る / not16、and16、or16、mux16

p.27
今度は多入力ゲートを作る。

not16 (16ビット入力、全ビットを否定して16ビット出力):

library ieee;
use ieee.std_logic_1164.all;

entity not16 is
    port (
        inp: in std_logic_vector(15 downto 0);
        outp: out std_logic_vector(15 downto 0)
    );
end entity;

architecture behavior of not16 is
begin
    outp <= inp nand x"FFFF";
end architecture;

and16 (16ビット同士のandをとる):

library ieee;
use ieee.std_logic_1164.all;

entity and16 is
    port (
        a, b: in std_logic_vector(15 downto 0);
        outp: out std_logic_vector(15 downto 0)
    );
end entity;

architecture behavior of and16 is
begin
    outp <= (a nand b) nand x"FFFF";
end architecture;

or16:

library ieee;
use ieee.std_logic_1164.all;

entity or16 is
    port (
        a, b: in std_logic_vector(15 downto 0);
        outp: out std_logic_vector(15 downto 0)
    );
end entity;

architecture behavior of or16 is
    signal not_a, not_b: std_logic_vector(15 downto 0);
begin
    not_a <= a nand x"FFFF";
    not_b <= b nand x"FFFF";
    
    outp <= not_a nand not_b;
end architecture;

mux16 (16ビット幅×2本のうちどちらかを出力する):

library ieee;
use ieee.std_logic_1164.all;

-- a, bのどちらかを出力する。
entity mux16 is
    port (
        a, b: in std_logic_vector(15 downto 0);
        sel: in std_logic;
        outp: out std_logic_vector(15 downto 0)
    );
end entity;

architecture behavior of mux16 is
begin
    mux: for i in 0 to 15 generate
        mux: entity work.mux
        port map (
            sel => sel,
            a => a(i),
            b => b(i),
            outp => outp(i)
        );
    end generate;
end architecture;