1の立っているビット数を数える / VHDL

1の立っているビット数を数える / Python -の続き

8ビットの場合のみ試す。

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity count_1s_in_8bits is
    port (
        inp: in std_logic_vector(7 downto 0);
        num_1s: out std_logic_vector(3 downto 0)
    );
end entity;

architecture behavior of count_1s_in_8bits is
    signal sute0, sute1, sute2: unsigned(7 downto 0) := (others => '0');
begin
    sute0 <= unsigned(inp);
    sute1 <= (sute0 and x"55") + (( '0' & sute0(7 downto 1)) and x"55");
    sute2 <= (sute1 and x"33") + (("00" & sute1(7 downto 2)) and x"33");
    num_1s <= std_logic_vector(sute2(3 downto 0) + sute2(7 downto 4));
end architecture;

テストベンチ:

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                
use ieee.numeric_std_unsigned.all;
use ieee.numeric_std.all;         

ENTITY count_1s_in_8bits_vhd_tst IS
END count_1s_in_8bits_vhd_tst;
ARCHITECTURE count_1s_in_8bits_arch OF count_1s_in_8bits_vhd_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL inp : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL num_1s : STD_LOGIC_VECTOR(3 DOWNTO 0);
COMPONENT count_1s_in_8bits
    PORT (
    inp : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    num_1s : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0)
    );
END COMPONENT;
BEGIN
    i1 : count_1s_in_8bits
    PORT MAP (
-- list connections between master ports and signals
    inp => inp,
    num_1s => num_1s
    );

    
process begin
    for i in 0 to 255 loop
        inp <= to_std_logic_vector(i, 8);
        wait for 10 ns;
    end loop;
    wait;
end process;   


END count_1s_in_8bits_arch;