nビット加算器 / リップルキャリーアダー

今度は前回の全加算器を任意の個数だけ数珠つなぎにしてリップルキャリーアダーを作る。リップルする様子が確認できるよう、最終段だけでなく全段のキャリーアウトを外部端子に接続しておく。

ファイル一式: VHDL_for_Quartus_Prime/n_bits_adder_ripple at main · ti-nspire/VHDL_for_Quartus_Prime · GitHub

トップレベルエンティティ:

library ieee;
use ieee.std_logic_1164.all;

entity n_bits_adder_ripple is
    generic (
        NUM_BITS: natural := 4
    );
    port (
        c0: in std_logic;
        x: in std_logic_vector(NUM_BITS-1 downto 0);
        y: in std_logic_vector(NUM_BITS-1 downto 0);
        
        cout: out std_logic_vector(NUM_BITS downto 1); -- リップルの様子が見えるよう端子に出しておく。
        s: out std_logic_vector(NUM_BITS-1 downto 0)
     );
end entity;

architecture rtl of n_bits_adder_ripple is
    signal c_inside: std_logic_vector(NUM_BITS downto 0);
begin

   --u1: for i in s'range generate
    u1: for i in 0 to NUM_BITS-1 generate
        fa: entity work.full_adder
        port map (
            cin => c_inside(i),
            x => x(i),
            y => y(i),
            cout => c_inside(i+1),
            s => s(i)
        );
    end generate;
    
    c_inside(0) <= c0;
    cout <= c_inside(NUM_BITS downto 1);

end architecture;

テストベンチ:

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;            
use ieee.numeric_std_unsigned.all;
use ieee.numeric_std.all;

ENTITY n_bits_adder_ripple_vhd_tst IS
END n_bits_adder_ripple_vhd_tst;
ARCHITECTURE n_bits_adder_ripple_arch OF n_bits_adder_ripple_vhd_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL c0 : STD_LOGIC;
SIGNAL cout : STD_LOGIC_VECTOR(4 DOWNTO 1);
SIGNAL s : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL x : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL y : STD_LOGIC_VECTOR(3 DOWNTO 0);
COMPONENT n_bits_adder_ripple
    PORT (
    c0 : IN STD_LOGIC;
    cout : OUT STD_LOGIC_VECTOR(4 DOWNTO 1);
    s : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    x : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    y : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
    );
END COMPONENT;
BEGIN
    i1 : n_bits_adder_ripple
    PORT MAP (
-- list connections between master ports and signals
    c0 => c0,
    cout => cout,
    s => s,
    x => x,
    y => y
    );

process begin
    for i in 0 to 15 loop
    for j in 0 to 15 loop
        c0 <= '0';
        x <= to_std_logic_vector(i, 4);
        y <= to_std_logic_vector(j, 4);
        wait for 10 ns;
    end loop;
    end loop;
    wait;
end process;    
    
END n_bits_adder_ripple_arch;

rtlシミュレーションなのでリップルの様子は観測できない。ところどころにハザードが出ている。