バイナリー→BCD変換函数を作る / double dabbleアルゴリズム / VHDL

pp.358-359

unsigned 12ビット値(0～4095)を4桁BCD値 (0,0,0,0～4,0,9,5)に変換する。

subprograms_pkg.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package subprograms_pkg is
    function binary_to_bcd (bin: std_logic_vector) return std_logic_vector;
end package;

package body subprograms_pkg is
    function binary_to_bcd (bin: std_logic_vector) return std_logic_vector is
        variable bcd: unsigned(15 downto 0) := (others => '0');
    begin
        for i in 11 downto 1 loop
            bcd := bcd(14 downto 0) & bin(i);
            if bcd(15 downto 12)>"0100" then bcd(15 downto 12):=bcd(15 downto 12)+"0011";end if;
            if bcd(11 downto  8)>"0100" then bcd(11 downto  8):=bcd(11 downto  8)+"0011";end if;
            if bcd( 7 downto  4)>"0100" then bcd( 7 downto  4):=bcd( 7 downto  4)+"0011";end if;
            if bcd( 3 downto  0)>"0100" then bcd( 3 downto  0):=bcd( 3 downto  0)+"0011";end if;
        end loop;
        bcd := bcd(14 downto 0) & bin(0);
        return std_logic_vector(bcd);
    end function;
end package body;

library ieee;
use ieee.std_logic_1164.all;
use work.subprograms_pkg.all;

entity test_circuit is
    port(
        clk : in  std_logic;
        inp : in  std_logic_vector(11 downto 0);
        outp: out std_logic_vector(15 downto 0)
    );
end entity;

architecture rtl of test_circuit is
begin
    process(clk)
    begin
        if rising_edge(clk) then
            outp <= binary_to_bcd(inp);
        end if;
    end process;
end architecture;

今0d3841をBCD (0011, 1000, 0100, 0001)に変換している。