A、B、OUTの各レジスタとPCとをVHDLで記述する

前回作った74161のようなものを使ってA、B、OUTの各レジスタとPCとを作る。4つとも1つにまとめる。

library ieee;
use ieee.std_logic_1164.all;

entity registers is
    generic(
        NUM_BITS: natural := 4
    );
    port(
        clk    : in std_logic;
        aclr_n : in std_logic;
        sload_n: in std_logic_vector(NUM_BITS-1 downto 0); -- a_reg:0, b_reg:1,out_reg:2, pc: 3
        
        from_74283: in std_logic_vector(NUM_BITS-1 downto 0);

        a_reg  : out std_logic_vector(NUM_BITS-1 downto 0);
        b_reg  : out std_logic_vector(NUM_BITS-1 downto 0);
        out_reg: out std_logic_vector(NUM_BITS-1 downto 0);
        pc     : out std_logic_vector(NUM_BITS-1 downto 0)
    );
end entity;

architecture rtl of registers is
begin

    a_register: entity work.generic_74161
        generic map(NUM_BITS => NUM_BITS)
        port map(
            clk     => clk,
            aclr_n  => aclr_n,
            sload_n => sload_n(0),
            d       => from_74283,
            p       => '0',
            t       => '0',
            q       => a_reg
        );

    b_register: entity work.generic_74161
        generic map(NUM_BITS => NUM_BITS)
        port map(
            clk     => clk,
            aclr_n  => aclr_n,
            sload_n => sload_n(1),
            d       => from_74283,
            p       => '0',
            t       => '0',
            q       => b_reg
        );

    out_register: entity work.generic_74161
        generic map(NUM_BITS => NUM_BITS)
        port map(
            clk     => clk,
            aclr_n  => aclr_n,
            sload_n => sload_n(2),
            d       => from_74283,
            p       => '0',
            t       => '0',
            q       => out_reg
        );

    program_counter: entity work.generic_74161
        generic map(NUM_BITS => NUM_BITS)
        port map(
            clk     => clk,
            aclr_n  => aclr_n,
            sload_n => sload_n(3),
            d       => from_74283,
            p       => '1',
            t       => '1',
            q       => pc
        );

end architecture;