メモリー / ram64を作る

Chapter 3

今度は前回のram8を8個束ねる。これだけでLEを5,000個近く消費する。今使っているFPGAではもう限界である。テキストはこのram64を8個束ねてram512を作り、ram512を8個束ねてram4kを作り、ram4kを4個束ねてram16kを作る。

library ieee;
use ieee.std_logic_1164.all;

entity ram64 is
    port (
        inp: in std_logic_vector(15 downto 0);
        clk: in std_logic;
        load: in std_logic;
        address: in std_logic_vector(5 downto 0);
        outp: out std_logic_vector(15 downto 0)
    );
end entity;

architecture behavior of ram64 is
    type load_t is array (0 to 7) of std_logic;
    signal temp_load: load_t;
    
    type reg_t is array (0 to 7) of std_logic_vector(15 downto 0);
    signal temp_reg_in: reg_t;
    signal temp_reg_out: reg_t;
    
begin
    u0: entity work.dmux8way
    port map (
        inp => load,
        sel => address(5 downto 3),
        a => temp_load(0),
        b => temp_load(1),
        c => temp_load(2),
        d => temp_load(3),
        e => temp_load(4),
        f => temp_load(5),
        g => temp_load(6),
        h => temp_load(7)
    );
    
    u1a: for i in 0 to 7 generate
        u1b: entity work.ram8
        port map (
            clk => clk,
            load => temp_load(i),
            inp => inp,
            address => address(2 downto 0),
            outp => temp_reg_out(i)
        );
    end generate;
        
    u2: entity work.mux8way16
    port map (
        a => temp_reg_out(0),
        b => temp_reg_out(1),
        c => temp_reg_out(2),
        d => temp_reg_out(3),
        e => temp_reg_out(4),
        f => temp_reg_out(5),
        g => temp_reg_out(6),
        h => temp_reg_out(7),
        sel => address (5 downto 3),
        outp => outp
    );
end architecture;

動作未確認。