自動クロックと手動クロックとを組み合わせてクロックジェネレーターを作る

前回、前々回の回路を組み合わせてクロックジェネレーターを作る。

library ieee;
use ieee.std_logic_1164.all;

entity clk_gen is
    generic(
        F_CLK: natural := 48_000_000;
        
        FREQ_LO: natural := 1;
        FREQ_HI: natural := 10;
        
        BOUNCE_msec: natural := 15;
        IS_INVERTED: boolean := true
    );
    port(
        clk          : in  std_logic;
        manual_clk_in: in  std_logic;
        sel          : in  std_logic_vector(1 downto 0);
        clk_out      : out std_logic
    );
end entity;

architecture rtl of clk_gen is
    signal manual_signal: std_logic;
    signal auto_signal  : std_logic;
begin
    manual: entity work.debouncer
        generic map(
            F_CLK       => F_CLK,
            BOUNCE_msec => BOUNCE_msec,
            IS_INVERTED => IS_INVERTED -- when pushed, Hi out; when released, Lo out.
        )
        port map(
            clk          => clk,
            bounce_in    => manual_clk_in,
            debounce_out => manual_signal
        );
    auto: entity work.auto_clk
        generic map(
            F_CLK   => F_CLK,
            FREQ_LO => FREQ_LO,
            FREQ_HI => FREQ_HI
        )
        port map(
            clk     => clk,
            sel     => sel(1), -- when 0, FREQ_LO out; when 1, FREQ_HI out
            clk_out => auto_signal
        );
        
        process(all)
        begin
            if rising_edge(clk) then
                case sel is
                    when "00"      => clk_out <= manual_signal;
                    when "01"|"10" => clk_out <= auto_signal;
                    when others    => clk_out <= '0';
                end case;
            end if;
        end process;

end architecture;