全加算器

全加算器を再度試す。半加算器を2個連結するのではなく下の回路にした。

library ieee;
use ieee.std_logic_1164.all;

entity full_adder is
    port (
        cin: in std_logic;
        x: in std_logic;
        y: in std_logic;
        
        cout: out std_logic;
        s: out std_logic
    );
end entity;

architecture logic of full_adder is
begin
    s <= x xor y xor cin;
    cout <= (x and y) or (x and cin) or (y and cin);
end architecture;

テストベンチ:

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

ENTITY full_adder_vhd_tst IS
END full_adder_vhd_tst;
ARCHITECTURE full_adder_arch OF full_adder_vhd_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL cin : STD_LOGIC;
SIGNAL cout : STD_LOGIC;
SIGNAL s : STD_LOGIC;
SIGNAL x : STD_LOGIC;
SIGNAL y : STD_LOGIC;
COMPONENT full_adder
    PORT (
    cin : IN STD_LOGIC;
    cout : OUT STD_LOGIC;
    s : OUT STD_LOGIC;
    x : IN STD_LOGIC;
    y : IN STD_LOGIC
    );
END COMPONENT;
BEGIN
    i1 : full_adder
    PORT MAP (
-- list connections between master ports and signals
    cin => cin,
    cout => cout,
    s => s,
    x => x,
    y => y
    );

process begin
    cin <= '0'; x <= '0'; y <= '0'; wait for 10 ns;
    cin <= '0'; x <= '0'; y <= '1'; wait for 10 ns;
    cin <= '0'; x <= '1'; y <= '0'; wait for 10 ns;
    cin <= '0'; x <= '1'; y <= '1'; wait for 10 ns;
    cin <= '1'; x <= '0'; y <= '0'; wait for 10 ns;
    cin <= '1'; x <= '0'; y <= '1'; wait for 10 ns;
    cin <= '1'; x <= '1'; y <= '0'; wait for 10 ns;
    cin <= '1'; x <= '1'; y <= '1'; wait;
end process;
    
    
END full_adder_arch;

Simplify[BooleanConvert[(\[Not]cin \[And] \[Not]x \[And] y) \[Or](\[Not]cin \[And] x \[And] \[Not]y) \[Or](cin \[And] \[Not]x \[And]\[Not]y) \[Or](cin \[And] x \[And] y)]]
BooleanConvert[(\[Not]cin \[And] x \[And] y) \[Or] (cin \[And] \[Not]x \[And] y) \[Or] (cin \[And] x \[And] \[Not]y) \[Or] (cin \[And] x \[And] y)]